1. Field of the Invention
This invention relates to integrated circuits and in particular to a testable latch for latching asynchronous signals, the latch being suitable for use in an integrated circuit.
2. Brief Description of the Prior Art
In the manufacture of microprocessors and other digital signal processors, it is essential to be able to test the functioning of the different parts of the circuit. The testing is typically achieved by providing in the processor an alternative set of interconnections among all the latches so that they are joined together to form a single shift register. In order to effect the testing, a pattern of 1's and 0's is stepped in through the shift register connection to set the latches to known states. The microprocessor is then reconfigured to its normal functional connections and is caused to operate normally for at least one clock cycle. After that the data stored in the latches is stepped out along the shift register path and compared with the output expected. In this way failure of the microprocessor to perform the required logical operations can be detected and the likely cause of such failures pinpointed in the device. This test also enables the ability of the latches to store both the "1" state and the "0" state satisfactorily to be checked satisfactorily.
In order to implement this testing operation each latch in the microprocessor must be provided with selectable inputs, at least one for its normal operation and at least another for connecting the latches together in the shift register configuration.
Some latches in many microprocessors are intended to respond to asynchronous inputs, for example, inputs which arise from outside the device. An asynchronous input takes the form of a SET signal on one conductor defining the transition to the "1" state and a CLEAR signal on another conductor defining the transition to the "0" state. Asynchronous signals are usually latched using a pair of cross-coupled NAND-gates to form a bistable element with separate SET and CLEAR inputs applied in inverted form to the two NAND-gates. Although it would be possible to connect such a latch into a shift register with other latches so that it could be tested in the manner described above, it would require a large amount of additional circuitry to provide the additional connections in the inputs to the latch required to produce the shift register configuration. Moreover, since the additional circuitry is required to produce the shift register configuration it cannot be tested independently of the latches.
It is an object of the present invention to provide a testable digital data storage circuit in which the above difficulties are substantially overcome.